Integrated self-aligned quadruple patterning flow for sub-7nm application

Device size shrinkage has been one of the most effective methods in the semiconductor industry for the purpose of cost reduction and performance enhancement. In order to achieve the size requirement at the nanometer level, there are several patterning techniques, such as extreme ultra violet lithography and self-aligned multi-patterning, which have attracted intensive attention from the industry. One of the most popular patterning methods is self-aligned multiple patterning (SAMP). This method relies on self-alignment of a sidewall spacer to transfer into desirable patterns. After transferring, the resulting patterns will have half the pitch of the original structure. The process can be repeated for additional pitch halving in term of size shrinkage. This method has been adapted for high volume production in the advance semiconductor technology node for the past several years. It provided supreme performance in terms of physical performance such as line width roughness (LWR) and critical dimension uniformity (CDU). However, due to the process complexity, this technique usually suffers the pitch walking effect and relatively high cost and long turn-around time compared with the direct patterning method. In this paper, we studied several integration flows for sub-30nm pitch line and space including 193i SAQP and EUV SADP schemes. A general cost analysis is performed to compare the differences in cost and number of processing steps. Besides the manufacturability, we summarized a comprehensive line and space performance comparison between these flows in term of physical performance (CD, LWR, LER and SWR) and the potential impact factors for pattern process control such as sidewall angle and step height.