Highly stackable Oxide-semiconductor Channel Transistor Technology for Future High-density and Low-power 3D DRAM

We demonstrate a highly stackable and ultra-low leakage oxide-semiconductor channel transistor technology for 3D Oxide-semiconductor Channel Transistor DRAM (OCTRAM). It uses a replacement-type InGaZnO cell transistor with a novel Channel-Side WL (CSWL) configuration designed for Z-pitch scaling. This approach reduces process cost and improves multi-tier compatibility by utilizing mature Oxide/Nitride (O/N) stacks and deposited channels. The 3D OCTRAM architecture, integrating both vertical bit line (VBL) and word line (WL) select transistors with replacement-type designs, enables more WL stacks and continuous bit density growth. The prototype cell transistor demonstrates a high on-current of over 30µA/cell and an excellent on-off ratio >10¹³ with a gate length (Lg) of 45 nm. An 8-layer stacked 3D OCTRAM cell transistor was successfully fabricated, confirming excellent transfer characteristics across all layers. We conclude that 3D OCTRAM is a promising candidate for future high-density, low-power 3D DRAM applications.