Wafer-to-Wafer Bonding Fabrication Process-Induced Wafer Warpage

Wafer warpage affects the resolution of photolithography, process alignment, and wafer bonding, which leads to the degradation of the device's yield, performance, and reliability. With the development of devices, the increase of metal layers in the stack direction will worsen the warpage problem. We investigate the Wafer-to-Wafer (W2W) bonding process-induced warpage issue with experiments and a full wafer simulation. A concave wafer warpage of $70~\mu \text{m}$ is observed for a single wafer with a $7.8~\mu \text{m}$ thickness DRAM layer due to the shrinkage of the DRAM layer. In both experiments and simulation, we reveal that the W2W bonding process induces warpage 3 times the single wafer warpage value, as the deformation restriction of the DRAM layers by the thinned Si layer is weak. Furthermore, good agreement is observed between the simulated results and the measured data, which validates the simulation mode. We estimate the wafer warpage of the multi-stack wafer bonding with the validated model. As an example, the warpage of a 4-stack wafer is revealed to be 7 times the single wafer warpage value. This study provides useful information on wafer warpage in the W2W bonding process and reveals the severe warpage issue with increasing the stacked metal layers.