Bias and Temperature Effects on DCR and RTS Fluctuations in 1- and 2-Layer CMOS SPADs

Single photon avalanche diodes (SPADs) fabricated in a 150 nm CMOS technology are characterized under different bias and temperature conditions. The device under test consists of a chip including arrays of SPADs with different active area and different avalanche quenching network, either passive or active. Both single-layer and dual-layer SPAD array configurations (the latter being based on the face-to-face interconnection of two virtually identical chips) are investigated. Measurements are focused on breakdown voltage and dark count rate (DCR) performance, with particular emphasis on DCR fluctuations of the random telegraph signal (RTS) kind.