Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm

In high-speed SerDes channels, it becomes more important to reduce impedance mismatches to minimize signal return. Most of the mismatches are due to the differential via on PCB which is essential component to make up the PCIe Gen 5 system, and this mismatch should be reduced for the high-speed signal quality. To effectively minimize the mismatch, this paper presents an equation based TDR estimation model of the differential via, and the model is verified to commercial model of the coupled transmission line. And this paper also proposes a method for optimizing the design parameters of the differential via by applying a reward based on TDR impedance to PSO algorithm. The optimization procedure is then applied to one of the actual PCB designs to verify the optimized design parameters.