Counter-based Eye-open Monitoring System Design for High-speed Serial Interface

An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. Through the estimated eye-opening information, the eye calculates the open area and the optimal sampling point. The size and phase of the sampling point are controlled by 5-bit, respectively. The proposed eye-open monitor was fabricated through a 180-nm CMOS process and consumes 86mW at a 2Gb/s data rate, 1.8V supply.