A 12-bit 10-GS/s Time-Interleaved ADC With Distortion-Cancelled Track-and-Hold Amplifier

This paper presents a 12-bit 10-GS/s time-interleaved (TI) ADC with distortion-cancelled track-and-hold amplifier (THA). A half-swing input buffer and ring amplifier (ringamp)-based output buffers are implemented to reduce THA nonlinearity and power consumption. Static and Dynamic distortion cancellation schemes are proposed to enhance THA linearity without imposing extra circuit loading on the buffers. These schemes leverage the opposite polarity of nonlinearities from each circuit component to realize cancellation—static distortion cancellation between the input buffer and output buffer, and dynamic distortion cancellation between the input buffer and sampling network. Fabricated in a 28-nm CMOS process, the prototype ADC consumes 198.1 mW, including 63.9 mW for the THA. At Nyquist input frequency, the ADC achieves 50.48-dB SNDR and 69.91-dB SFDR, equivalent to a Walden FoM of 72.6 fJ/conv.-step and a Schreier FoM of 154.5 dB, demonstrating outstanding linearity and power efficiency.