Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power

This paper proposes a novel strategy for power reduction at logic level. Our approach tries to suppress unnecessary output transitions due to internal and external don't cares by using weakly complementary MOS gates. Treating the conductive condition for pMOS network and the one for nMOS network of each gate separately and explicitly, don't cares for each of pMOS network and nMOS network of a gate is evaluated, and pMOS network and nMOS network is shown to be modified separately, which contributes the suppression of output transitions of the gate.