An Off-Chip Capacitor-Less LDO Design with Low Noise and High PSRR

In this paper, a low dropout regulator (LDO) with low noise and high PSRR is designed based on 55 nm CMOS process. The output noise of the LDO is reduced by designing a low-noise error amplifier with a new structure, the feed-forward ripple cancellation (FFRC) technique is used to improve the PSRR of the LDO by incorporating FFRC at the supply voltage and the gate of the power transistor, which also pushes the gate pole of the power transistor to high frequencies, thus improving the loop stability of the system. With an output voltage of 1.4 V, the PSRR is -64 dB at low frequencies and -52 dB at 400 KHz, the output noise is 14 nV/sqrt (Hz) at 100 KHz.