Modeling of the impact of mechanical stress resulted from wafer probing and wire bonding on circuit under pad

Circuit Under Pad (CUP), also known as Bond Pad Over Active (BPOA), has been gaining popularity in the semiconductor industry. However, such a design concept amplifies the effect of stress-inducing processes, which are detrimental to the chip's electrical performance and mechanical reliability. The said processes are wire bonding and wafer probing, and they are unavoidable in the manufacturing of a semiconductor. Although the Finite Element Analysis (FEA) of these processes has been carried out in previous research, the focus was not on the polysilicon resistor or metallization layers in CUP, but on the bond pad only. On the other hand, wire bonding is carried out after wafer probing in the manufacturing line. However previous studies, either numerically or experimentally, investigated the processes separately. Specifically, those studies did not link the stress and deformation history of the wafer-CUP structure resulting from the wafer probing to the stress and deformation induced in the subsequent wire bonding process. Therefore, this project scoped both simulations in a continuous manner and using a CUP design as the chip's structure. ANSYS Mechanical was utilized to simulate the dynamic wafer probing and thermosonic wire bonding. The result showed that copper bonding exerted more stress compared to gold bonding. Meanwhile, the Cu/low-k chip is more sensitive to stress-inducing factors than the Al/SiO2 chip.