An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC

Over the past decade, SAR ADCs have extended their territory to higher resolution with noise-shaping (NS). lncorporated with a pipeline architecture, the conversion speed could also be improved. However, as the accuracy requirements for the residue amplifier (RA) in the pipeline architecture are often very costly, several techniques have been reported to avoid power and gain-calibration burden on the RA: The gain-error shaping (GES) technique [1] shapes the quantization leakage error caused by the RA gain-error, but some additional analog components and digital processing are required. The 2-0 MASH structure [2] has an inherent RA gain-error tolerance, but the possible mismatch between the analog and the digital NTFs would limit the performance as in typical MASH DSMs. Motivated by the issues mentioned above, this paper introduces a $2^{\mathrm{n}\mathrm{d}}-$order noiseshaping interpolating-SAR (NS ISAR) ADC for the backend ADC in dual-residue (D-R) pipeline architecture [3], where there is no RA gain accuracy burden. A Segmentation technique for the capacitive interpolating DAC is also proposed to enhance the achievable resolution (+20dB SONR improvement) by solving the parasitic sensitiveness of the capacitive interpolation. With the RA burden alleviated in power, calibration, and linearity, the prototype pipeline ADC in a 180nm CMOS process achieves an SNDR of 81. 2dB in a 1. 5MHz BW at an OSR of 8 without any calibration.