Bonding of silicon wafers for silicon-on-insulator

Several aspects of a new silicon-on-insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10-s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal-oxide-semiconductor (MOS) capacitors. The results were consistent with a negative charge density at the bond interface of approximately 1011 cm−2. A double-etch-back procedure was used to thin the device wafer to the desired thickness with ±20 nm thickness uniformity across a 4-in. wafer. The density of threading dislocations in the remaining silicon layer was 102 –103 cm−2, and the residual dopant concentration less than 5×1015 cm−3, both remnants of the etchstop layer. Complimentary metal-oxide-semiconductor (CMOS) devices made in the 20–100 nm silicon thick layers had subthreshold slopes of 68 mV/decade (both n- and p-channel MOS transistors). The effective carrier lifetime was 15–20 μs in 80- and 300-nm-thick Si films and the interface state density at the Si film-buried oxide interface was ≤5×1010 cm−2.