逐次逼近ADC
过采样
比较器
CMOS芯片
电子工程
噪声整形
交错
计算机科学
功率消耗
三角积分调变
有效位数
电压
电气工程
工程类
功率(物理)
物理
量子力学
作者
Takashi Matsukawa,Takuji Miki,Kazuo Matsukawa,Yoji Bando,Takeshi Okumoto,Koji Okihara,Shiro Sakiyama,Shiro Dosho
标识
DOI:10.1109/isscc.2013.6487731
摘要
SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge, which is one of the reasons for the 105mW power consumption at 12.5MS/s. In [2], 8× oversampling and a static current pre-amplifier for the comparator improve SNR to 88dB, but the ADC still consumes 66mW. In [3], digital calibration achieves an SNDR of 71dB at 3mW, but double conversion limits the sampling speed to 22.5MS/s.This paper describes a SAR ADC with 71dB SNDR that runs at 50MS/s and consumes 4.2mW. The ADC uses 3 SNDR-enhancement techniques that utilize noise and that have good compatibility to low-voltage fine digital processes.
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