Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs

This paper presents approximate multiplier architectures which are efficiently deployed on Field Programmable Gate Arrays (FPGAs). Our approximate multipliers offer higher gains of energy-area products than those of the state-of-the-art works with comparable accuracies. Moreover, our approximate multipliers are more energy-area efficient than a Look-up table based Intellectual Property (IP) multiplier provided by an FPGA vendor. Finally, a real-life image processing application (e.g., image multiplication) is realized by using the proposed approximate multipliers to demonstrate their applicability and effectiveness. Experimental results show that our proposed multiplier saves up to 45.0% power dissipation compared to the exact IP multiplier and can achieve a high peak signal-to-noise ratio of 45.34 dB.