Power efficient multiplier using Vedic algorithm and self bias transistor technique

We live in a digital world surrounded by digital content in the form of images, videos, and much more which consume extensive power. With the extensive use of digital content in portable gadgets power consumption has been critical issue to act upon. The multiplier is the core component used in image processors and digital signal processors and by altering the properties of the multiplier system provides superior performance. In this work, we analyse the combined effect of the Self-Bias Transistor (SBT) Technique and Vedic multiplication algorithm on a multiplier unit realised using reduced transistor technique on conventional adders and CMOS array Multiplier units. Simulation results display the 76.5%, 80.15% and 84.21% drop in power consumption of 4-bit, 8-bit and 16-bit SBT based Vedic multiplier at 45 nm technology node respectively. The effectiveness of the proposed technique is also presented at 100 nm and 65 nm technology nodes. Further, the effect of the SBT-based Vedic multiplier on the delay and power-delay product is explored at 100 nm, 65 nm and 45 nm technology. It is found that SBT-based multipliers are power efficient on Gate Diffusion Input-based multipliers