Common Source Line-to-Word Line Short Improvement by Eliminating SLT Sidewall Notch in 3D NAND Deep Trench Patterning

A failure electrical case caused from high leakage current between common source lines (CSL) and word-lines (WL) in 3D NAND is reported in this paper. Physical failure analyses (PFA) of leakage path revealed direct physical shorting between deep slit trench (SLT) and vertical channels (VC), and the hot spot delayer from its surface to the bottom by plasma focused ion beam (PFIB) exposed more and more abnormal notching profiles along SLT sidewalls toward VC. It is suspected that charges existing in the VC affecting the plasma trajectory could be the cause. The abnormal profiles can be successfully eliminated through optimizing etch recipe and optioning specific hardware configuration of the etching chamber. As a result, the failure item attributed to WL leakage is suppressed with >95% of pass ratio for device operation.