电源完整性
计算机科学
功率分析
信号完整性
设计流量
功率(物理)
可靠性工程
炸薯条
嵌入式系统
功率流
功率优化
集成电路设计
电子工程
印刷电路板
电力系统
工程类
操作系统
电信
物理
密码学
量子力学
计算机安全
功率消耗
标识
DOI:10.1109/edaps.2015.7383714
摘要
Power integrity (PI) co-analysis of Chip-package-system (CPS) is a powerful tool to accomplish the extremely challenging goal; lower cost but better performance. However, the conventional PI analysis of CPS using chip power model (CPM) has limitations on the design evaluation and optimization of board and package. In this paper, we demonstrate the limitation first and share our experience on the development of PI analysis flow using Extended CPM (ECPM) technique on CPS to overcome the limitation.
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