Challenges in integration of metal gate high-k dielectrics gate stacks

The methodology and various challenges of fabrication of sub 1 nm metal gate high k FETs are reviewed. Aggressively scaled metal gated-HfO 2 MOSFETs can be scaled below 1 nm using chemical oxides interface with only 5 A . General improvement in V T instability of sub 1 nm metal gated-HfO 2 devices are observed as a result of EOT scaling. With a 5 A interfacial oxide layer, the electron mobility of sub 1 nm metal gated-HfO 2 is observed to be severely degraded with EOT scaling in gate last transistor flows.