Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors

A novel and practicable partial punch-through-stopper (p-PTS) scheme beneath the gate area is proposed for the substrate leakage current suppression in the gate-all-around (GAA) nanosheet field-effect transistors (NSFETs). Thanks to the weakened electric field and widened tunneling length caused by the lightly doped substrate under the drain region, this p-PTS scheme can not only achieve a low PT current comparable to the conventional full-PTS (f-PTS) scheme, but also substantially reduce the BTBT current of drain–substrate junction by about two orders of magnitude. Moreover, the key parameters of the p-PTS scheme, such as p-PTS doping concentration (Np-PTS), thickness (Tp-PTS) and width (Wp-PTS), are systematically optimized and analyzed. As a result, compared to the conventional f-PTS scheme, p-PTS scheme exhibits a larger process window and better immunity of leakage current to process variations. The above results indicate that the proposed p-PTS scheme is one of the most promising methods for suppressing substrate leakage current in NSFET.