A High-throughput Hardware Implementation of ZUC-256 Stream Cipher

The ZUC-256 stream cipher algorithm has been incorporated into the security portfolio of 3GPP LTE-Advanced. Therefore, it is important to study its high-performance implementation. In this paper, we present a high-throughput hardware implementation of the ZUC-256 cryptographic algorithm for ASICs and FPGAs. By using a fully pipelined design scheme, the critical path of the algorithm in both operating modes is significantly shortened and the operating frequency is increased. The throughput of ZUC-256 is up to 160Gpbs with the area 15500GEs under TSMC 12nm technology. In comparison with other work, the area efficiency of the ASIC implementation is improved by 1.61 times and that of FPGA is improved by 1.06 times while the throughput rate is significantly improved.