锡
光刻胶
图层(电子)
符号
材料科学
涂层
蚀刻(微加工)
数学
算法
纳米技术
冶金
算术
作者
Tao Huang,Run-Ling Li,Han-Lun Cai,Zhao-Yang Li,Yu-Long Jiang
标识
DOI:10.1109/ted.2023.3241271
摘要
In this work, from the viewpoint of process integration the threshold voltage ( ${V}_{t}$ ) variation for multi- ${V}_{t}$ FinFETs fabricated by changing work function metal (WFM) TiN thickness is investigated. Four kinds of WFM thickness are prepared by the combination of three times atomic layer deposition (ALD) and three times wet etching of TiN layers. In the whole four- ${V}_{t}$ process integration scheme, it is revealed that the ${V}_{t}$ variation is very large for N-FinFET with only one layer of TiN. It is further observed that this TiN layer is partially eroded, although it should be protected by a photoresist during wet etching. It is proposed and demonstrated that the additional high-temperature prebaking treatment before spin-coating of the bottom anti-reflection coating (BARC) on the TiN surface can reduce the unexpected erosion of the TiN layer coated by photoresist, resulting in the effective suppression of ${V}_{t}$ variation.
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