A Compact Model for Interface-Type Self-Rectifying Resistive Memory With Experiment Verification

Resistive random access memory (RRAM), a new non-volatile memory, enables hardware accelerators based on in-memory computing with improved throughput and energy efficiency, enabling machine learning on-the-fly inference at the edge. However, sneak-path currents in RRAM crossbar arrays (CBAs) can cause crosstalk, limiting high-density applications. The best choice for suppressing leakage current is self-rectifying RRAM (SRR). Interface-type RRAMs offer CMOS compatibility, better controllability, higher reliability, and lower power consumption compared to filament-type counterparts. However, while there is much research on the filament-type RRAMs, there is little research and no measurement validation on the interface-type RRAMs. In this paper, a compact model of the interface-type RRAM is developed for circuit and system exploration. The model includes Schottky barrier diode, effective layer resistance, nano-battery effect, parasitic resistance, and capacitance. It also has a dynamic behavior model, including device-to-device variation, retention, and endurance. Compared with measurements, it reproduces high accuracy of 98.97% in DC and 98.05% in AC. The proposed model is applied to a neuromorphic $64\times64$ SRR CBA with 32-bit fixed-point precision. A nano-battery bias scheme is also proposed to zero the current of RRAMs having non-zero I-V crossing points, reducing the sneak-pass current error to 0.02%. A vector matrix multiplication application demonstrates 3.44 TOPS/W with a 50:50 LRS to HRS ratio, and a deep neural network on a VGG-8 architecture using the CIFAR-10 dataset observes an accuracy degradation of 1.36%.