CMOS芯片
电流(流体)
模式(计算机接口)
光电子学
计算机科学
电气工程
电子工程
材料科学
工程类
操作系统
作者
B.O. Lim,Hanhee Jo,Jaeduk Han
标识
DOI:10.1109/isocc59558.2023.10396410
摘要
This paper compares two prominent high-speed link transmitter driver topologies, cascode current-mode logic (CML) and tailless CML, exploring their design tradeoffs. Analysis and simulation results reveal that the cascode CML exhibits higher output resistance due to the presence of a tail current source, while the tailless CML demonstrates faster operation with reduced output capacitance. Additionally, this study highlights the tradeoff between driver output swing and power consumption.
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