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The design and qualification of the TEL CLEAN TRACK ACTTMM photomask coating tool at Intel

抵抗 涂层 光掩模 薄脆饼 GSM演进的增强数据速率 计算机科学 工艺工程 制造工程 机械工程 工程制图 工程类 材料科学 纳米技术 电信 图层(电子)
作者
Andrew Jamieson,Thuc Dam,Ki‐Ho Baik,Ken Duerksen,Elie Eidson,Keiji Akai,Kazuya Hisano,Norifumi Kohama,Shinichi Machidori
出处
期刊:Proceedings of SPIE [SPIE]
被引量:2
标识
DOI:10.1117/12.681751
摘要

As photomask complexity has increased, mask manufacturing has become significantly more challenging. Tightening specs on defect performance, resolution, and CD control have pushed mask manufacturing to achieve levels that nearly match wafer capabilities. To meet wafer manufacturing needs, mask production requires high yield and quick turn-around time, resulting in an increased demand for very high equipment reliability. In-line resist coating capability is important to meet these demands; both for robust 2nd level phase-shift coating processes, and the enablement of advanced 1st-level process development with new resists and new resist process conditions. Intel Corporation worked with Tokyo Electron Ltd (TEL) to bring one of the first CLEAN TRACK ACT M (ACT M) units through design, acceptance tests and into manufacturing. TEL's CLEAN TRACK ACT M is a resist coating tool based on the CLEAN TRACK ACT12 (ACT 12) wafer manufacturing platform, and contains multiple mask-specific modules including advanced softbake oven units, edge-bead removal modules, and cleaning systems. After setup and optimization, the tool shows impressive performance, (for example, within-plate thickness uniformity of < 8A (3s) for certain processes). The motivation of the tool layout is discussed thoroughly. Elements of the module designs and their performance are shown. The acceptance testing performance is presented and includes: cleaning capabilities, oven performance, thickness performance, coating defect levels and edge bead removal capabilities. Finally, there is a limited discussion of manufacturing performance.

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