Stacked DRAM Solution: Multilayer Horizontal Cell (MHC) 1T1C DRAM

Stacked dynamic random access memory (DRAM) technology has garnered considerable attention as a means to continue the relentless pursuit of scaling. In this context, we have developed a five-layer horizontal cell with vertical word line (WL) and pillar capacitor to realize a stacked DRAM architecture. This design boasts an excellent combination of highon-state andoff-state current ratio (${I}_{\text {on}}$/${I}_{\text {off}}\text {)}$of ~1E8, a steep subthreshold slope (SS) of ~93 mV/dec and a moderate threshold voltage (${V}_{t}\text {)}$of 0.76 V. A novel process integration scheme incorporating boron silicate glass (BSG)/phosphorus silicate glass (PSG) capping doping, double gate formation, channel thickness optimization, and device electrical engineering considerations are presented and discussed. Moreover, we have also explored the feasibility of fabricating a 64-layer structure through the development of critical unit processes. This study suggests a promising approach using multilayer horizontal cells (MHCs) to further advance the scaling of DRAM technology.