比较器
CMOS芯片
磁滞
晶体管
传播延迟
电压
电子工程
功率延迟产品
施密特触发器
比较器应用
电气工程
功率(物理)
阈值电压
计算机科学
材料科学
工程类
物理
量子力学
作者
Abhay S. Vidhyadharan,Gangavarapu Anuhya,Shivangi Shukla,Sanjay Vidhyadharan
标识
DOI:10.1080/03772063.2023.2165176
摘要
This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.
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