A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators

This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, the 8.5–17.8-GHz output is covered and the phase noise is reduced by about 3 dB with the halving total equivalent inductance of the tank. Meanwhile, the clock distribution is designed to obtain 0.05–8.9-GHz output. By using the retiming and separate division techniques, frequency coupling is solved, and the implementation of the clock distribution is separated from its noise considerations, which alleviates design complexity. Fabricated in 65-nm CMOS process, the proposed CPPLL is verified, and it achieves −109.9-dBc/Hz@1 MHz phase noise and −71.6-dBc reference spur at 16-GHz output. The integrated jitter is 144 fs from 10 kHz to 100 MHz.