A Temperature-Dependent dVCE/dt Model for Field-Stop IGBT at Turn-Off Transient

In this article, an analytical model is proposed to model collector-emitter voltage rising slope (dVCEdt) of field-stop insulated gate bipolar transistor (FS IGBT) during the turn-off transient. Thanks to TCAD simulation, the internal physics of the FS IGBT during VCE rise transient is investigated. Based on the improved understanding of the VCE rise transient, an analytical solution of the excess carrier distribution in the N-base region and field-stop (FS) layer is derived. An analytical model for dVCE/dt of FS IGBT is also proposed. The temperature dependency of various silicon material and device parameters is included in the model. In the end, the double-pulse tests are performed on 650-V/40-A and 1200-V/40-A FS IGBTs. The test results are compared with the analytical predictions and good agreement is obtained.