A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit

A 256-Mb gate-all-around (GAA) 6T SRAM is implemented in Samsung 3GAE EUV technology. Adaptive dual-bitline (ADBL) and adaptive cell-power (ACP) SRAM assist schemes are proposed to reduce SRAM $V_{\mathrm {MIN}}$ . ADBL reduces the effective bitline (BL) resistance up to 62% by connecting auxiliary bitline (AUXBL) of small resistance to BL in the write operation. ACP performs write assist by selecting a farther power switch from the accessed bitcell to improve write margin with the increased cell-power resistance. Silicon shows that both ADBL and ACP improve $V_{\mathrm {MIN}}$ by 230 mV.