Energy Optimization of Tapered Buffers for CMOS On-Chip Switching Power Converters

This work presents a model to determine the power consumption of tapered buffers, validating its results with transistor-level simulations. Focusing on their application as gate drivers for high-frequency on-chip switching power converters, the need for a fall-rise time evaluation at the output of the tapered buffer is discussed. Consequently, the output fall-rise time is modeled and validated by means of simulations. Given the linear relation between the fall-rise time and the switching losses of the power MOSFET, an optimized design procedure is proposed to concurrently minimize the switching losses of the tapered buffer together with the power MOSFET switching losses. The work concludes with a design example for a 15000 /spl mu/m-width PMOS transistor, presenting an optimum tapering factor of 21, for a specific 0.35 /spl mu/m standard CMOS technology.