计算机科学
节点(物理)
无线
计算机硬件
嵌入式系统
电信
工程类
结构工程
作者
Lee J Johnson,W.R. Eisenstadt,F. Alexander,Kyle T. Packer
出处
期刊:IEEE Access
[Institute of Electrical and Electronics Engineers]
日期:2021-01-01
卷期号:9: 108702-108717
标识
DOI:10.1109/access.2021.3101734
摘要
In the development of small scale, networked nodes, design inspiration can be found in the decentralized and simplistic communication used by starlings in flight. Here, we present a novel node processor based on simple nearest neighbor connections to yield a self-organized linear optical sensor network. We present the processor state machine design and evaluation of the Verilog code. Each node, termed a MicroSTARLING, contains a processor fabricated using 180nm CMOS technology. The chips are 1.2mm ×1.2mm and the digital processor occupies 0.063 mm 2 of the chip. We assemble three test bench nodes to evaluate the processor function in wired, wireless communication and fully wireless circuits. When nodes are directly wired, the MicroSTARLING processor functions with a 25MHz input clock enabling a linear multihop network readout of 8 devices in 1.8ms. With a 20 μW, 524KHz input clock, the processor requires 12 μW at 1.2V. We evaluate the processor function under optical communication obtaining 6-hops between 7 nodes with little noticeable reduction in communication quality. Our fully wireless node required 3mW of power harvested via a 940nm light emitting diode (LED) and communicated via separate LEDs. To our knowledge this is the first demonstration of more than 3 hops of linear wireless communication with a mm scale self-organizing node processor. The processor size and power make possible the concept of smart dust networks with multihop communication between nodes for an embedded wireless sensor network in biological tissue structures or as the foundation of an optical neural network for edge computing.
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