High Operation Density Logic‐Gates for Multi‐Bit Arithmetic Logic Unit Based on Multi‐Region Barrier Modulation Optoelectronic Transistor

ABSTRACT The ever‐increasing computational demands of artificial intelligence matrix calculations are driving breakthrough hardware designs for edge computing. However, this progress is significantly constrained by the high transistor consumption. Here, a novel logic architecture with an ultrahigh computation density based on a multi‐region gate transistor is proposed. Benefitting from the unique ability of multi‐region barrier modulation, the consumption of transistors in our full‐logic gate unit is less than 10 % of traditional circuits. In addition, owing to the transistor possessing exceptional electrical characteristics, e.g., a switching ratio of 2.62 × 10 7 , an ultra‐low off‐state current of 32 fA, and a minimized subthreshold swing of 92.25 mV/dec, a high‐performance arithmetic logic unit (ALU) multi‐bit edge computing system based on the 4 × 8 Field‐Programmable Gate Array (FPGA) is constructed using these multi‐region gate transistors. The FPGA not only executes 8‐bit cryptographic operations directly at the network edge near end‐users, but also can be dynamically reconfigured into two independent 2‐bit full adders with carry propagation for parallel arithmetic processing. It can effectively redistribute the computational burden away from cloud resources. This work will pave the way for designing the ultra‐compact circuit for further highly efficient Internet of Things (IoT) ecosystems with energy efficiency.