EUV pupil optimization for 32nm pitch logic structures

A pupil optimization was carried out for the M2 layer of the imec N7 (foundry N5 equivalent) logic design. This is exposed as a single print EUV layer. We focused on the printability of the toughest parts of the design: a dense line space grating of 32 nm pitch and a tip-tip grating of 32 nm pitch, tip-to-tip target CD of 25 nm. We found that the pupil optimization can improve both the line space and the tip-to-tip gratings energy latitude and depth of focus. The tip-to-tip target CD can be pushed further, enabling further design scaling.