Minimal Switching Loss Three-Stage Active Gate Driving Strategy Based on Dynamic dv/dt Switching Model for GaN HEMT

The fast switching of gallium nitride high mobility transistor (GaN HEMT) results in high dv/dt and severe EMI issues, requiring a trade-off with the switching power loss. Three-stage gate drive (TSGD) can mitigate the conflict between switching speed and losses, but it is challenging to achieve minimal switching loss under the existing TSGD strategy due to the nonlinear parasitic capacitance of GaN HEMT. To address this issue, this article proposes a minimal switching loss TSGD strategy based on a dynamic dv/dt switching (DVTS) model, which can achieve minimal switching loss. First, based on the charge conservation principle, piecewise linear equivalent values for the parasitic capacitances of GaN HEMT are calculated. Based on the result, analytical expressions for the transient voltage and current in each switching stage are derived, which forms the DVTS model and provides detailed analysis for the dv/dt nonlinearity. Furthermore, analytical expressions for switching loss during each stage are calculated, establishing the quantitative relationship between switching loss and drive conditions. By minimizing the total loss, the required driving currents and switching timings are determined. Finally, the MSL-TSGD strategy is proposed. Experimental results demonstrate that the proposed method reduces the turn-on loss by 18.6%, and reduces the turn-on delay by 29.3%.