MOL Local Interconnect Innovation: Materials, Process & Systems Co-optimization for 3nm Node and Beyond

In this paper, we present a newly developed selective tungsten gap-fill process and its optimization. The optimized selective tungsten gap-fill process offers a liner-less, bottom-up, seamless tungsten growth with 40% via-resistance reduction over traditional CVD tungsten vias. Our ring-oscillator modeling projects a 6% and 13% ring-oscillator performance benefit at 7 nm and 3 nm technology nodes respectively and a 4% processor-level performance benefit at 7 nm node. Overall, selective tungsten is the most advanced process innovation targeting MOL resistance scaling for 3 nm logic nodes and beyond.