Multi-objective Design Space Exploration for High-Level Synthesis via Bayesian Optimization

High-level Synthesis (HLS) becomes popular since it can improve productivity of circuit designs. The optimization of HLS is necessary since the design space is vast and different configurations can lead to various power, performance and area (PPA). In this paper, we model the design space exploration (DSE) as a multi-objective black-box optimization problem via Bayesian optimization with float encoding method to explore the Pareto front of HLS designs for PPA objectives, where Multi-objective Tree-structured Parzen Estimator (MOTPE) is adopted as the surrogate model which can search the tree-structured design space efficiently and Expected Hypervolume Improvement (EHVI) is used as the acquisition function to guide the optimization. The experimental results show that our method achieves LPDA gains by 66.30% and 41.25%, compared with two meta-heuristic algorithms, simulated annealing (SA) and NSGA-II. Our learned Pareto front is closer to the reference Pareto front than SA and NSGA-II, with an average improvement in ADRS by 94.72% and 69.58% respectively.