A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology

This paper presents a 28-Gb/s full-rate NRZ bang-bang clock and data recovery (CDR) in 22 nm FD-SOI CMOS technology. In order to reduce supply voltage and power dis-sipation, class-AB current-mode logic (CML) and forward-body biasing (FBB) are extensively used. Furthermore, the clock driver and clock path in the bang-bang phase detector are carefully optimized. The circuit operates reliably in a wide range of supply voltages from 0.8 to 1.2 V without adjustment of the body biasing. The CDR core dissipates 27.2mW at 0.8V supply voltage and 54.4 mW at 1.2 V supply voltage. The recovered full-rate data surpasses jitter tolerance with a good margin (BER less than 10– ¹² ) over the entire supply voltage range. A figure-of-merit (FoM) of 0.97 mW/ Gb/s for 0.8 V supply voltage is achieved. This FoM represents the best FoM for full-rate NRZ bang-bang CDRs above 20 Gb/s and compares reasonably well with high-speed half-rate and quarter-rate NRZ CDR FoM $s$ .