比较器
逐次逼近ADC
CMOS芯片
逆变器
数学
计算机科学
电子工程
电气工程
电压
工程类
作者
Xiaofeng Guo,Run Chen,Zhenqi Chen,Bin Li
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2023-03-01
卷期号:58 (3): 624-633
被引量:3
标识
DOI:10.1109/jssc.2022.3222162
摘要
This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at ±1/4 LSB. In addition, an open-loop inverter-based residue amplifier (RA) is proposed with simple circuit implementation. The RA gain is well defined by $g_{m}$ ratio and is immune to process, voltage, and temperature (PVT) variations. Fabricated in 40-nm CMOS technology, the prototype ADC achieves a mean signal-to-noise plus distortion ratio (SNDR) of 59.8–62.8 dB, with 1- $\sigma $ than 1.7 dB, at 600–625 MS/s over −40° to 125° temperature range and 1.1–1.2 V power supply range, a 67 dB dynamic range (DR), and a 62.4 dB SNDR for a Nyquist input while sampling at 625 MS/s. The overall power consumption is 7.05 mW.
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