薄脆饼
电弧
材料科学
GSM演进的增强数据速率
蚀刻(微加工)
光电子学
可靠性(半导体)
中心(范畴论)
工程物理
纳米技术
计算机科学
工程类
电极
化学
结晶学
物理
电信
物理化学
功率(物理)
量子力学
图层(电子)
作者
Jun Wang,Yuan Li,Xinruo Su
标识
DOI:10.1109/cstic55103.2022.9856849
摘要
In 40nm and sub-40nm manufacturing process, inter metal dielectric thickness shrink for process requirement, as a result, arcing defect on wafer during plasma etch start attract interests of researchers. Arcing defect, result from violent charge release process, occur on wafer edge usually. However, wafer center arcing is not a common phenomenon. In this paper, we report an arcing defect occur on wafer center and proposed a possible formation mechanism. Furthermore, a solution is also proposed and proven in both yield and reliability.
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