Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET

The influence of the number of bias levels for realizing capacitorless dynamic random access memory (DRAM) in nanowire (NW) gate-all-around (GAA) reconfigurable transistor (RFET) is analyzed through simulations. Although a careful selection of bias levels can enhance retention (1.8 s at 85 °C), reduce energy consumption ( $\sim $ 0.3 fJ), and enhance current ratio (CR) ( $\sim 10^{{5}}$ ) in NW GAA RFET, bias-induced word line (WL) and bitline (BL) disturbance in an array can limit 1T-DRAM performance. It is shown that NW GAA RFET DRAM exhibits immunity from all six BL disturbances up to 5 ms while WL disturbance is critical as three out of six possible cases are disturbed.