Precise Inner Spacer Etch-Back By Combining Ozone Gas Bake and Wet Chemical Etching

Introduction Beyond nanosheet technology in gate-all-around (GAA) transistor, Forksheet and Complementary FET (CFET) are proposed [1-4], and inner spacer formation is one of the most critical processes to electrically segregate nanosheet channel from source and drain. In this process sacrificial SiGe layers in multilayer structure are recessed, then inner spacer material is deposited on fin sidewall and etched back (Fig. 1). Accurate etch amount control and good uniformity from bottom to top of the structure are required for the etch back, and they become more challenging in CFET since number of inner spacer per fin increases as PMOS and NMOS are vertically stacked. As a solution, we developed digital etch by combining ozone bake and wet etching aiming to ALE-like etching by self-limiting oxidation and selective dissolution of oxidized inner spacer material. Experimental Three different types of inner spacer material and SiN as reference were used as etching test sample. Blanket film of each material was deposited to 300 mm Si wafer by ALD. The sample was processed with 0.15 % dilute HF to remove native oxide. After baked at 240 °C with 100 g/m 3 ozone ambient for 15 to 120 s, the sample was processed with 0.15 % dilute HF for 30 s to etch oxidized inner spacer materials. Etching amount was characterized by ellipsometry measuring pre and post process thickness. This cyclic process of ozone bakes, wet etch and the characterization were repeated 3 times to check controllability of etching amount. Results/Discussion Etching amount of inner spacer materials with ozone bake and dilute HF shows 0.5-2.5 nm while etching amount with sole dilute HF shows 0.03-0.25 nm (Fig. 2). SiN also shows 0.04 nm etching amount of dilute HF in both with and without ozone bake. These results suggest that ozone bake oxidized inner spacers then dilute HF removed the oxidized inner spacer selective to non-oxidized inner spacer and SiN which is base material of gate spacer and BDIs/MDIs. Fig. 3 shows etching amount is saturated with ozone bake time in 3 inner spacer materials. We assumed that O radical react at surface of inner spacer material and oxide grows in the initial phase, and then the oxidation stops when it reached to a certain thickness because O radical deactivated in the oxide film during diffusion. This self-limiting process is preferable characteristic considering etching uniformity of both within wafer and local bottom to top inner spacer. Fig. 4 shows linear relationship in 3 inner spacer materials between etching amount and the cycle number of digital etch combining ozone bake and wet etching. This ALE-like etching is also preferable for accurate etching amount control. Conclusion Inner spacer etch back is one of critical processes for Nanosheet and CFET integration. Digital etching with ozone bake and wet etching shows self-limiting process and ALE-like etching. These features are expected to enable precise inner spacer etch-back for future device fabrication beyond N3. References [1] Luc van den Hove, ITF world 2023. [2] M. Radosavljevic et al., IEDM 2023, 29-2. [3] J. Park et al., IEDM 2023, 29-4. [4] S. Liao et al., IEDM 2023, 29-6. Figure 1