作者
Laurent Brunet,P. Batude,C. Fenouillet-Béranger,P. Besombes,L. Hortemel,F. Ponthenier,B. Prévitali,C. Tabone,A. Royer,C. Agraffeil,C. Euvrard-Colnat,A. Seignard,Christophe Morales,Frank Fournel,L. Benaissa,Thomas Signamarcheix,P. Besson,Marine Jourdan,R. Kachtouli,V. Benevent,J.-M. Hartmann,C. Comboroure,N. Allouti,N. Possémé,C. Vizioz,C. Arvet,S. Barnola,S. Kerdilès,L. Baud,L. Pasini,C.-M. V. Lu,F. Deprat,A. Toffoli,G. Romano,C. Guedj,V. Delaye,F. Bœuf,O. Faynot,M. Vinet
摘要
For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.