平面的
材料科学
沟槽
光电子学
MOSFET
阻塞(统计)
电压
绝缘体上的硅
阈值电压
随时间变化的栅氧化层击穿
电气工程
栅氧化层
纳米技术
晶体管
硅
计算机科学
图层(电子)
工程类
计算机图形学(图像)
计算机网络
作者
Takashi Ishida,Tetsu Kachi,Jun Suda
标识
DOI:10.35848/1347-4065/aca266
摘要
Abstract To evaluate the impact of gate structures on the switching performance ( R on Q g ) and cost (required chip size, proportional to R on A ) of GaN vertical MOSFETs, we calculated the R on AR on Q g of trench-gate structures with and without a countermeasure to reduce the electric field applied to the gate insulator, as well as a planar structure with various cell pitches, channel mobilities, and blocking voltages. When the blocking voltage was 600 V, the planar-gate structure achieved the lowest R on AR on Q g owing to its low Q g / A , despite the high R on A . However, when the blocking voltage was 1800 V, a trench-gate structure without the countermeasure achieved the lowest R on AR on Q g owing to its low R on A and optimal cell pitch. The R on AR on Q g of a trench-gate structure with a countermeasure and planar-gate structure became close with increasing channel mobility. This indicates that high channel mobility is the most important factor, rather than the selection of the device structure.
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