Process Development and Reliability of Super-Size Embedded Silicon Fan-out Package with size 40mm*40mm

The rapid development of terminal application fields such as smartphones, wearables, new energy vehicles, the Internet of Things and high-performance computing has pushed chip packaging forward in the direction of miniaturization, multi-function, fast heat dissipation, low power consumption, and high bandwidth. In this context, fan out packaging has risen rapidly, and many technical branches have been derived. In this work, based on the embedded silicon fan out (eSiFO) packaging technology, a super-size eSiFO with a package size of 40mm*40mm was developed. The test vehicle we designed integrates four large chips of 14mm*14mm, the redistribution layer (RDL) line width and line spacing are 15um/15um, and the number of I/Os is as high as 2676. We have developed a chip picking and chip attaching technology suitable for large size chips, which significantly reduces the chip damage ratio and improves the voids in chip attaching process. We have also developed dual image exposure technology, surface mounted technology (SMT) and underfill process for super-size eSiFO package. The package-level and board-level reliability tests of super-size eSiFO were systematically studied, and the key factors affecting the results of reliability were found, and the failure analysis was carried out.