Optimized Crosstalk and Impedance Design for HBM3 Channels in InFO

This article aims to optimize the signal integrity of high-bandwidth memory (HBM) interconnects in silicon interposer layer that connect the memory and SoC (CPU, GPU). Based on the second-generation enhanced version of high-bandwidth memory (HBM2e), a new wiring layout with greatly reduced coupling coefficient is proposed to mitigate the crosstalk problems. Then, by taking advantage of mismatched source and load impedances, the optimized characteristic impedance of the interconnects is designed to achieve the best eye diagram for the latest third-generation high-bandwidth memory (HBM3). As a result, the eye opening of the original HBM2E can be improved from 11% to 51%, or 4.6 times improvement, for the high-speed transmission at 6.4GHz with risetime 15ps.