绝缘体上的硅
外延
分子束外延
材料科学
光电子学
制作
硅
量子点
限制
纳米技术
平面的
图层(电子)
计算机科学
医学
机械工程
替代医学
计算机图形学(图像)
病理
工程类
作者
Johannes Aberl,Lada Vukŭsić,Frank Fournel,Jean‐Michel Hartmann,Moritz Brehm
标识
DOI:10.1002/pssa.202200145
摘要
Quantum devices based on holes confined in crystalline Ge nanostructures have emerged as a promising platform in the field of quantum technology. Epitaxial Ge hutwires (HWs) successfully used in pioneering quantum bit (qubit) experiments are the logical next choice for long‐distance coherent spin–spin coupling experiments. However, leakage currents are currently limiting the device performance of HWs on bulk Si substrates. This drawback can be mitigated by the HW growth on silicon‐on‐insulator (SOI) substrates. Herein, molecular beam epitaxy (MBE) HW growth developed on technologically relevant SOI substrates with different device layer thicknesses is shown. Using atomic force microscopy characterization, the fabrication of HWs on SOI with lengths of up to 600 nm is demonstrated. In addition, the very narrow window of growth parameters for which successful HW growth can be achieved and the distinct differences of HW growth on SOI versus bulk Si substrates are addressed.
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