Single-Event Response of 22-nm Fully Depleted Silicon-on-Insulator Static Random Access Memory

We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previous partially depleted technology generations (32 and 45 nm). The per-bit cross section is approximately an order of magnitude lower than the previous generations with a higher onset linear energy transfer (LET). No dependence on roll angle or input pattern was found. Tilt angle data follow the cosine law. Increasing the SRAM array supply voltage from the minimum tested 0.73 V to the maximum 1.08 V decreases SEE sensitivity by as much as 8%. Decreasing the p-well voltage from the nominal 0 V to the maximum -2 V increases the SEE cross section by as much as 2×. The n-well voltage has little effect on the SEE sensitivity due to the specifics of the transistor layout in the SRAM. Changing both the n- and p-well voltages simultaneously results in identical results as when only the p-well voltage was changed.