Warpage Simulation and Experimental Validation of the X-Dimension Fan-Out Integration-Bridge Wafer Level Packaging Process

In this paper, the full wafer level packaging process flow of a novel large $x$-dimension fan-out integrationbridge ($\text{XDFOI}^{\text{TM}}$) die chip is introduced. The warpage values of its full manufacturing process are investigated by finite element analysis and validated by manufacturing test data. To simulate the full packaging process flow warpage and consider the influence of residual strain and stress at each step, the element birth and death technique is introduced to the finite element analysis (FEA) model with an equivalent structure and material parameters by theoretical method to equivalently simplify the structure of redistribution layer (RDL). The reference temperature of RDL are recalculated too. The viscoelastic material model of Epoxy Molding Compound (EMC) is used to simulate the curing process. This full process warpage simulation results at several packaging steps are validated by warpage test data which showing the accuracy between simulation and test data is above 75 %. Furthermore, this paper discusses the key measures to reduce the wafer level packaging process warpage values from various aspects such as material CTEs matching, elastic modulus of glass carrier, etc. The method introduced in this paper can be used to predict and reduce the wafer level packaging process warpage of an advanced packaging structure.