Multiobjective Optimization for Heat Transfer Performance of Micro-Fins and Signal Integrity of Key Interconnect Technologies in 3-D Integrated Chips

This article is devoted to the synergistic design of the thermal management and signal integrity for 3-D integrated chips. The structure parameters of the micro-fin and interconnected components are optimized to obtain a balanced performance of chip heat dissipation and signal integrity. The 3-D integrated chip flows heat transfer model under the action of electrothermal coupling is developed. A full-wave electromagnetic simulation model of the signal interconnection components is proposed with the same structural parameters. The effects of various structural factors on the heat transfer performance and signal integrity of 3-D integrated chips are investigated. A multiobjective optimization algorithm is carried out to simultaneously reduce the total thermal resistance of the 3-D integrated chip and the signal transmission losses of the critical interconnect components. The results show that the total thermal resistance of the 3-D IC becomes lower with a larger through-silicon via (TSV) diameter, micro-fins height and micro-fin radius, and smaller oxide thickness. When the TSV diameter and oxide thickness increase, the height and radius of the micro-fins are reduced to facilitate the signal transmission of the chip's interconnected components. The response surface analysis method was used to design the experimental combination and thus obtain the fit function for the performance of the two objectives. Hundred sets of Pareto optimal solutions are obtained by multiobjective optimization. The technique for order preference by similarity to ideal solution (TOPSIS) method is used to select the weights of the two optimization objectives to determine the optimal solution. When thermal resistance and signal transmission are given equal weight in the chip design, thermal resistance is reduced by 13.8%, and signal transmission efficiency is improved by 9.74%. The study has important implications for chip thermal management and signal integrity.