An Efficient Hardware Implementation of CNN Generic Processor for FPGA

Convolutional Neural Networks (CNNs) have gained significant popularity in recent years due to their exceptional performance in classification tasks. However, the large number of computational operations that are needed for these models can limit their practicality. Field Programmable Gate Arrays (FPGAs) can be a promising solution for accelerating CNNs as they give the ability to create custom hardware designs. In this paper, we present an efficient hardware implementation for the CNN processor, in which a generic processor is designed and implemented to accelerate CNNs on hardware with the minimum number of operations and hardware resources. Our target is to reduce the number of needed memory and Digital Signal Processor blocks (DSP) to allow full implementation in FPGA on-chip memory. Multiple optimization techniques were used, such as loop unrolling, weights pruning, and quantization, to achieve our target. The processor is evaluated on the LeNet5 architecture using the MNIST dataset on the Vertix-7 FPGA, which showed a 17.9x reduction in weights size and very competitive performance-to-resources efficiency when compared with literature.